Electronics 1: cram pack

Formula sheets, the key method steps for every topic and 14 practice problems, with full solutions at the back.

New problemsBack to the course

In the print window, choose “Save as PDF” to keep a copy on your device.

1Formulas and methods

Diodes & transistors

Diode (constant drop)
VD = 0.7 V when conducting
Active region
VBE = 0.7 V, IC = β·IB, IE = (β + 1)·IB
Fixed bias
IB = (VCC − 0.7)/RB
Divider bias
IB = (VTH − 0.7)/(RTH + (β + 1)RE)
Thévenin of the divider
VTH = VCC·R2/(R1 + R2), RTH = R1∥R2
Collector loop
VCE = VCC − ICRC − IERE
Saturation
IC(sat) = (VCC − VCE(sat))/RC, IB ≥ IC(sat)/β

Op-amp circuits

Inverting amplifier
Vout = −(Rf/Rin)·Vin
Non-inverting amplifier
Vout = (1 + Rf/R1)·Vin
Summing amplifier
Vout = −Rf(V1/R1 + V2/R2)
Ideal op-amp
V+ = V−, Iin = 0

RC & RL transients

Time constant
τ = RC | τ = L/R
Response
x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ
Capacitor at DC
open circuit; vC cannot jump
Inductor at DC
short circuit; iL cannot jump
Settled
t ≈ 5τ

Method

  1. Find the initial value just after switching: a capacitor voltage and an inductor current cannot jump.
  2. Find the final value long after switching: a capacitor acts as an open circuit, an inductor as a short circuit.
  3. Find the time constant: τ = RC or τ = L/R, using the resistance seen by the capacitor or inductor.
  4. Use x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ.

Series & parallel resistors

Resistors in series
Req = R1 + R2 + …
Resistors in parallel
1/Req = 1/R1 + 1/R2 + …
Two in parallel
Req = R1R2 / (R1 + R2)
Ohm's law
V = I·R
Power
P = V·I = I²R = V²/R

Method

  1. Start at the end of the network furthest from the terminals.
  2. Combine resistors in series by adding them, and resistors in parallel with 1/R = 1/R₁ + 1/R₂ + …
  3. Redraw the circuit after each step.
  4. Repeat until one resistor is left between the terminals.

DC-DC converters

Buck
Vo = D·Vin
Boost
Vo = Vin/(1 − D)
Inverting buck-boost
|Vo| = Vin·D/(1 − D)
Ideal power balance
VinIin = VoIo
Inductor ripple
ΔIL = VL,on·D/(L·f); buck Vin − Vo, boost and buck-boost Vin
Average inductor current
buck Io; boost and buck-boost Io/(1 − D)
Output ripple
buck ΔIL/(8fC); boost and buck-boost Io·D/(fC)
CCM boundary
buck (1 − D)R/(2f); boost D(1 − D)²R/(2f); buck-boost (1 − D)²R/(2f)

Method

  1. Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
  2. Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
  3. Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
  4. For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.

Wheatstone bridge & strain gauges

Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε

Method

  1. Treat the bridge as two voltage dividers across the same supply.
  2. For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
  3. For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
  4. For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

2Practice problems

1.Diodes & transistorsMedium
RC​ = 5.6 kΩβ = 200IC​ = ?RE​ = 2.2 kΩVCC​ = 12 VR1​ = 39 kΩR2​ = 15 kΩ

An NPN transistor with β = 200 has voltage-divider bias from VCC = 12 V: R₁ = 39 kΩ from VCC to the base and R₂ = 15 kΩ from the base to ground. The collector resistor is RC = 5.6 kΩ and the emitter resistor is RE = 2.2 kΩ. Take VBE = 0.7 V and use the Thévenin equivalent of the divider (do not neglect the base current). Find the collector current IC in mA.

VCC = 12 VR1 = 39 kΩR2 = 15 kΩRC = 5.6 kΩRE = 2.2 kΩβ = 200
IC = mA
2.Diodes & transistorsHard
RC​ = 150 Ωβ = 50IC​ = ?VCC​ = 9 V3.3 VRB​ = 10 kΩ

An NPN transistor with β = 50 switches a 150 Ω load resistor connected between VCC = 9 V and its collector. The emitter is grounded. The base is driven from a 3.3 V logic output through a base resistor RB = 10 kΩ. Take VBE = 0.7 V and VCE(sat) = 0.2 V. Find the collector current IC in mA when the input is high. Decide first whether the transistor is saturated.

VCC = 9 VRC = 150 Ωβ = 50Vin = 3.3 VVBE = 0.7 VVCE(sat) = 0.2 VRB = 10 kΩ
IC = mA
3.Op-amp circuitsMedium
−+Vout​R2​ = 47 kΩV1​ = 1.2 VR1​ = 100 kΩV2​ = −1.4 VR3​ = 100 kΩR4​ = 47 kΩ

The difference amplifier uses an ideal op-amp with ±15 V supplies, with R3 = R1 and R4 = R2. Find the output voltage Vout.

V1 = 1.2 VV2 = −1.4 VR1 = R3 = 100 kΩR2 = R4 = 47 kΩ
Vout = V
4.Op-amp circuitsHard
Vin​V1​Vout​stage 1: invertingR1​ = 2 kΩRf1​ = 4.7 kΩstage 2: non-invertingR2​ = 1 kΩRf2​ = 2 kΩ

Two ideal op-amp stages are connected in cascade: an inverting amplifier (R1, Rf1) followed by a non-inverting amplifier (R2 to ground, Rf2 in the feedback). Both run from ±15 V supplies. Find the overall voltage gain Av = Vout/Vin.

R1 = 2 kΩRf1 = 4.7 kΩR2 = 1 kΩRf2 = 2 kΩ
Av =
5.RC & RL transientsMedium
R = 20 Ωt = 0L22 mHi(t)

The inductor carries a steady current of 3 A. At t = 0 the switch closes the loop through R and the source is removed, so the inductor current decays through R. Find the voltage vR across R at t = 1 ms.

i(0) = 3 AR = 20 ΩL = 22 mHt = 1 ms
vR = V
6.RC & RL transientsHard
+−Vs​12 Vt = 0R = ?C2.2 µF+−vC​

A timer starts charging an uncharged capacitor through a resistor from a 12 V supply at t = 0. It must trigger when the capacitor voltage reaches 10.8 V, exactly 25 ms after the start. With C = 2.2 µF, find the resistance R needed.

Vs = 12 VVth = 10.8 VT = 25 msC = 2.2 µF
R = kΩ
7.Series & parallel resistorsMedium
R1​ = 8 ΩR3​ = 15 Ω+−V1​6 VR2​10 ΩAR4​3 ΩB

Find the equivalent resistance Req seen by the source V1.

V1 = 6 VR1 = 8 ΩR2 = 10 ΩR3 = 15 ΩR4 = 3 Ω
Req = Ω
8.Series & parallel resistorsHard
R1​ = 20 ΩR3​ = 3 ΩR5​ = 20 Ω+−V1​5 VR2​2 ΩAR4​15 ΩBR6​25 Ω

Find the equivalent resistance Req seen by the source V1.

V1 = 5 VR1 = 20 ΩR2 = 2 ΩR3 = 3 ΩR4 = 15 ΩR5 = 20 ΩR6 = 25 Ω
Req = Ω
9.DC-DC convertersMedium
tiL​Imax​ = ?Imin​Io​DTT2T

A buck converter turns 9 V into 3.6 V for a 2 Ω load. It switches at 25 kHz with L = 100 µH. Find the peak inductor current Imax.

Vin​ = 9 VVo​ = 3.6 Vf = 25 kHzL = 100 µHR = 2 Ω
Imax = A
10.DC-DC convertersHard
tiL​Imax​IL​DTT2T

An ideal boost converter turns 9 V into 15 V for a 2 Ω load at 50 kHz. Find the smallest inductance Lcrit for continuous conduction.

Vin​ = 9 VVo​ = 15 Vf = 50 kHzR = 2 Ω
Lcrit = µH
11.Wheatstone bridge & strain gaugesMedium
+−3 V150 Ω150 Ω + ΔR150 Ω150 Ωab+−7.46 mV

A bridge with four 150 Ω arms is supplied with 3 V. When the sensor R₂ changes, the output reads Vab = 7.46 mV. Find the exact change ΔR of R₂.

Vs = 3 VR = 150 ΩVab = 7.46 mV
ΔR = Ω
12.Wheatstone bridge & strain gaugesHard
+−2.5 V350 Ω350 Ω + ΔR350 Ω350 Ωab+−Vo​

A quarter bridge (one active gauge, GF = 2.1) is excited with 2.5 V. The largest strain to be measured is 800 µε, and it must give 2.5 V at the input of an analogue-to-digital converter. Find the amplifier gain G.

Vs = 2.5 VGF = 2.1εmax = 800 µεVFS = 2.5 V
G =
13.Digital logic: gates, K-maps & flip-flopsMedium
ABCD000111100001111011111

In this Karnaugh map exactly one 1 has no neighbouring 1, so it stays a group of one cell (a full minterm of four literals) in the minimal SOP form. Neighbours across the map edges count. Click that cell.

F = Σm(0, 3, 9, 11, 15)
  1. 1AB = 00, CD = 00
  2. 2AB = 00, CD = 01
  3. 3AB = 00, CD = 11
  4. 4AB = 00, CD = 10
  5. 5AB = 01, CD = 00
  6. 6AB = 01, CD = 01
  7. 7AB = 01, CD = 11
  8. 8AB = 01, CD = 10
  9. 9AB = 11, CD = 00
  10. 10AB = 11, CD = 01
  11. 11AB = 11, CD = 11
  12. 12AB = 11, CD = 10
  13. 13AB = 10, CD = 00
  14. 14AB = 10, CD = 01
  15. 15AB = 10, CD = 11
  16. 16AB = 10, CD = 10
14.Digital logic: gates, K-maps & flip-flopsHard
ABCD00011110000111100001130214X50706X121131151140809X11110

For F(A, B, C, D) = Σm(3, 4, 10, 13, 14, 15) + d(5, 11, 12), where d marks the don't-care conditions, find the number N of essential prime implicants.

F(A, B, C, D) = Σm(3, 4, 10, 13, 14, 15) + d(5, 11, 12)
N =

3Solutions

1.Diodes & transistors

Answer: IC = 1.163 mA

BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.

Thévenin equivalent of the divider

VTH = 12·15/(39 + 15) = 3.333 V
RTH = 39·15/(39 + 15) = 10.83 kΩ

Base current

KVL around the base loop; the emitter current is (β + 1)·IB.

IB = (3.333 − 0.7)/(10.83 + 201·2.2) = 5.813 µA

Collector current

IC = 200·5.813 µA = 1.163 mA
IE = 201·5.813 µA = 1.168 mA

Answer

IC = 1.163 mA
2.Diodes & transistors

Answer: IC = 13 mA

BJT as a switch: to switch a load fully on, the transistor is driven into saturation, where VCE = VCE(sat) and the collector current is set by the load: IC(sat) = (VCC − VCE(sat))/RC. Saturation needs at least IB = IC(sat)/β. If the base current is smaller, the transistor stays active and IC = β·IB.

Base current

IB = (3.3 − 0.7)/10 kΩ = 260 µA

Saturated or active?

β·IB is smaller than IC(sat), so the transistor stays active.

β·IB = 13 mA
IC(sat) = (9 − 0.2)/150 = 58.67 mA

Collector current

IC = β·IB = 13 mA

Answer

IC = 13 mA

The transistor is active, so the load is not fully switched on.

3.Op-amp circuits

Answer: Vout = −1.222 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Voltage at the inputs

R₃ and R₄ carry the same current, so they form a voltage divider; feedback makes V₋ = V₊.

V₊ = V2·R4/(R3 + R4) = −1.4·47/(100 + 47) = −0.4476 V
V₋ = V₊

KCL at the inverting input

(1.2 − −0.4476)/100 = (−0.4476 − Vout)/47
Vout = (R2/R1)·(V2 − V1) = (47/100)·(−1.4 − 1.2) = −1.222 V

Answer

Vout = −1.222 V
4.Op-amp circuits

Answer: Av = −7.05

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Gain of each stage

A1 = −Rf1/R1 = −4.7/2 = −2.35
A2 = 1 + Rf2/R2 = 1 + 2/1 = 3

Overall gain

Av = A1·A2 = −2.35·3 = −7.05

Answer

Av = −7.05
5.RC & RL transients

Answer: vR = 24.17 V

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Time constant

τ = L/R = 22 mH / 20 Ω = 1.1 ms

Decay of the current

i(t) = 3·e−1/1.1 = 1.209 A
vR = R·i = 20·1.209 = 24.17 V

Answer

vR = 24.17 V
6.RC & RL transients

Answer: R = 4.935 kΩ

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Required time constant

10.8 = 12·(1 − e−25/τ) → τ = 25/ln(12/(12 − 10.8))
τ = 25/2.303 = 10.86 ms

Resistance

kΩ times µF gives milliseconds.

R = τ/C = 10.86/2.2 = 4.935 kΩ

Answer

R = 4.935 kΩ
7.Series & parallel resistors

Answer: Req = 14.43 Ω

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 8 ΩR3​ = 15 Ω+−V1​6 VR2​10 ΩAR4​3 ΩB

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R3 + R4 = 15 + 3 = 18 Ω
R2 ∥ 18 = 10·18/(10+18) = 6.429 Ω
Req = R1 + 6.429 = 8 + 6.429 = 14.43 Ω

Answer

Req = 14.43 Ω
8.Series & parallel resistors

Answer: Req = 21.75 Ω

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 20 ΩR3​ = 3 ΩR5​ = 20 Ω+−V1​5 VR2​2 ΩAR4​15 ΩBR6​25 Ω

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R5 + R6 = 20 + 25 = 45 Ω
R4 ∥ 45 = 11.25 Ω
R3 + 11.25 = 14.25 Ω
R2 ∥ 14.25 = 1.754 Ω
Req = R1 + 1.754 = 20 + 1.754 = 21.75 Ω

Answer

Req = 21.75 Ω
9.DC-DC converters

Answer: Imax = 2.232 A

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 3.6/9 = 0.4

Average and ripple current

Io = 3.6/2 = 1.8 A
ΔIL = VL·D/(L·f) = 5.4·0.4/(100·10⁻⁶·25·10³) = 0.864 A

Peak current

Imax = 1.8 + 0.864/2 = 2.232 A

Answer

Imax = 2.232 A
10.DC-DC converters

Answer: Lcrit = 2.88 µH

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 1 − 9/15 = 0.4

Boundary condition

Set the average inductor current equal to half the ripple current and solve for L.

Lcrit = D(1 − D)²·R/(2f)

Critical inductance

Lcrit = 0.4(1 − 0.4)²·2/(250·10³) = 2.88 µH

Answer

Lcrit = 2.88 µH
11.Wheatstone bridge & strain gauges

Answer: ΔR = 1.499 Ω

Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.

Node voltage

Va = 1.5 + 0.00746 = 1.507 V

Solve the divider

R₂ = 150·1.507/(3 − 1.507) = 151.5 Ω
ΔR = 151.5 − 150 = 1.499 Ω

Answer

ΔR = 1.499 Ω
12.Wheatstone bridge & strain gauges

Answer: G = 2381

Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.

Bridge output at full scale

Vo = 1.05 mV

Gain

G = 2.5/0.00105 = 2381

Answer

G = 2381
13.Digital logic: gates, K-maps & flip-flops

Answer: AB = 00, CD = 00

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

Neighbours of each 1

A 1 with a neighbouring 1 can join a group of two or more.

m0: m1, m2, m4, m8 → 0
ABCD000111100001111011111

The isolated 1

m0 = A′B′C′D′ → AB = 00, CD = 00

Answer

AB = 00, CD = 00
14.Digital logic: gates, K-maps & flip-flops

Answer: N = 3

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

Prime implicants

The largest groups that can be formed from 1s and Xs.

BC′, B′CD, AC, AB
ABCD00011110000111100001130214X50706X121131151140809X11110

Essential prime implicants

BC′, B′CD, AC
N = 3

Answer

N = 3

ExamProblems · examproblems.com/courses/electronics-1