Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
A 6.2 V Zener regulator is fed from 15 V through 100 Ω and supplies a 1500 Ω load. Find the Zener current IZ.
Vin = 15 VVZ = 6.2 VR = 100 ΩRL = 1500 Ω
IZ = mA
2.Diodes & transistorsHard
An NPN transistor with β = 50 switches a 150 Ω load resistor connected between VCC = 9 V and its collector. The emitter is grounded. The base is driven from a 3.3 V logic output through a base resistor RB. Take VBE = 0.7 V and VCE(sat) = 0.2 V. For reliable switching, design for a base current 3 times the minimum needed for saturation. Find RB in kΩ.
The source Vₛ charges the capacitor through R₁, and R₂ is connected in parallel with C. The capacitor is uncharged when the switch closes at t = 0. Find the capacitor voltage vC at t = 40 ms.
Vs = 30 VR1 = 3.3 kΩR2 = 1 kΩC = 33 µFt = 40 ms
vC = V
6.RC & RL transientsHard
A timer starts charging an uncharged capacitor through a resistor from a 15 V supply at t = 0. It must trigger when the capacitor voltage reaches 11.25 V, exactly 1000 ms after the start. With R = 2.2 kΩ, find the capacitance C needed.
Vs = 15 VVth = 11.25 VT = 1000 msR = 2.2 kΩ
C = µF
7.Series & parallel resistorsMedium
Find the current IR2 through R2.
V1 = 12 VR1 = 12 ΩR2 = 4 ΩR3 = 4 ΩR4 = 10 Ω
IR2 = A
8.Series & parallel resistorsHard
Find the equivalent resistance Req seen by the source V1.
A bridge has four 350 Ω arms and Vs = 6 V. The sensor R₂ increases by ΔR = 70 Ω. Find the exact output Vab in mV.
Vs = 6 VR = 350 ΩΔR = 70 Ω
Vab = mV
12.Wheatstone bridge & strain gaugesHard
A 1000 Ω strain gauge with gauge factor 2.12 is bonded to a steel bar. Under load its resistance rises by 0.53 Ω. Find the strain ε in microstrain (µε).
Simplify F = BC + AB + A′B′C′ + A′BC′ to its minimal sum-of-products form. How many literals L does the simplified expression contain?
F = BC + AB + A′B′C′ + A′BC′
L =
14.Digital logic: gates, K-maps & flip-flopsHard
Find the minimal SOP form of F(A, B, C, D) = Σm(2, 3, 5, 11, 12) + d(7, 8, 14), where d marks the don't-care conditions. How many literals L does it contain?
F(A, B, C, D) = Σm(2, 3, 5, 11, 12) + d(7, 8, 14)
L =
3Solutions
1.Diodes & transistors
Answer: IZ = 83.87 mA
Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.
Resistor current
IR = 8.8/100 = 88 mA
Load current
IL = 6.2/1500 = 4.133 mA
Zener current
IZ = 88 − 4.133 = 83.87 mA
Answer
IZ = 83.87 mA
2.Diodes & transistors
Answer: RB = 0.7386 kΩ
BJT as a switch: to switch a load fully on, the transistor is driven into saturation, where VCE = VCE(sat) and the collector current is set by the load: IC(sat) = (VCC − VCE(sat))/RC. Saturation needs at least IB = IC(sat)/β. If the base current is smaller, the transistor stays active and IC = β·IB.
Collector current in saturation
IC(sat) = (9 − 0.2)/150 = 58.67 mA
Minimum base current
IB(min) = IC(sat)/β = 58.67/50 = 1173 µA
Design base current
IB = 3·1173 µA = 3520 µA
Base resistor
RB = (3.3 − 0.7)/IB = 2.6 V/3.52 mA = 0.7386 kΩ
Answer
RB = 0.7386 kΩ
3.Op-amp circuits
Answer: Vout = −1.279 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Input currents
V₋ = 0, so each input resistor has its full input voltage across it.
I1 = V1/R1 = 0.3/1 = 0.3 mA
I2 = V2/R2 = 0.5/4.7 = 0.1064 mA
If = I1 + I2 = 0.4064 mA
Answer
If = 0.4064 mA
5.RC & RL transients
Answer: vC = 5.539 V
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Thévenin equivalent seen by the capacitor
Short the source to find Rth; open the capacitor to find the voltage it will settle at.
Rth = R1 ∥ R2 = 3.3·1/(3.3 + 1) = 0.7674 kΩ
vC(∞) = 30·1/(3.3 + 1) = 6.977 V
Time constant
τ = Rth·C = 0.7674·33 = 25.33 ms
Charging curve
vC(t) = 6.977·(1 − e−40/25.33) = 5.539 V
Answer
vC = 5.539 V
6.RC & RL transients
Answer: C = 327.9 µF
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 4 + 10 = 14 Ω
R2 ∥ 14 = 4·14/(4+14) = 3.111 Ω
Req = R1 + 3.111 = 12 + 3.111 = 15.11 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 12/15.11 = 0.7941 A
Current through R₂
Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.
VA = V1 − IR1·R1 = 12 − 0.7941·12 = 2.471 V
IR2 = VA/R2 = 2.471/4 = 0.6176 A
Answer
IR2 = 0.6176 A
8.Series & parallel resistors
Answer: Req = 16.41 Ω
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 6 + 5 = 11 Ω
R4 ∥ 11 = 4.632 Ω
R3 + 4.632 = 16.63 Ω
R2 ∥ 16.63 = 4.409 Ω
Req = R1 + 4.409 = 12 + 4.409 = 16.41 Ω
Answer
Req = 16.41 Ω
9.DC-DC converters
Answer: ΔIL = 1.021 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 24/48 = 0.5
Inductor voltage during the on-time
While S is on, the inductor sits between Vin and Vo.
VL = 48 − 24 = 24 V
Ripple current
ΔIL = VL·D/(L·f) = 24·0.5/(47·10⁻⁶·250·10³) = 1.021 A
Answer
ΔIL = 1.021 A
10.DC-DC converters
Answer: ΔVo = 34.09 mV
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 9/15 = 0.6
Inductor ripple current
ΔIL = (15 − 9)·0.6/(330·10⁻⁶·20·10³) = 0.5455 A
Output ripple
ΔVo = 0.5455/(8·20·10³·100·10⁻⁶) = 34.09 mV
Answer
ΔVo = 34.09 mV
11.Wheatstone bridge & strain gauges
Answer: Vab = 272.7 mV
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Node voltages
Va = 6·420/770 = 3.273 V
Vb = 3 V
Output
Vab = 272.7 mV
Answer
Vab = 272.7 mV
The linear estimate Vs·ΔR/(4R) = 300 mV is 10 % too high: a quarter bridge is not quite linear.
12.Wheatstone bridge & strain gauges
Answer: ε = 250 µε
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Relative resistance change
ΔR/R = 0.53/1000 = 0.00053
Strain
ε = 0.00053/2.12 = 0.00025 = 250 µε
Answer
ε = 250 µε
13.Digital logic: gates, K-maps & flip-flops
Answer: L = 3
Boolean algebra: the rules that simplify expressions are X + X′ = 1 and X·X′ = 0, X + X = X, absorption X + X·Y = X, the combining rule X·Y + X·Y′ = X, X + X′Y = X + Y and the consensus theorem XY + X′Z + YZ = XY + X′Z. De Morgan's laws turn (X·Y)′ into X′ + Y′ and (X + Y)′ into X′·Y′. A Karnaugh map applies these rules graphically: every group of two neighbouring cells is one use of XY + XY′ = X.
Minterms of the expression
BC → m(3, 7)
AB → m(6, 7)
A′B′C′ → m(0)
A′BC′ → m(2)
Group and read off
F = B + A′C′
Count the literals
L = 3
Answer
L = 3
14.Digital logic: gates, K-maps & flip-flops
Answer: L = 12
Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.
Prime implicants
The largest groups that can be formed from 1s and Xs.
B′CD, A′CD, AC′D′, A′BD, ABD′, A′B′C
Minimal cover
F = B′CD + AC′D′ + A′BD + A′B′C
L = 12
Answer
L = 12
Another grouping of the same size exists; it has the same number of terms and literals.