Electronics 1: cram pack

Formula sheets, the key method steps for every topic and 14 practice problems, with full solutions at the back.

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1Formulas and methods

Diodes & transistors

Diode (constant drop)
VD = 0.7 V when conducting
Active region
VBE = 0.7 V, IC = β·IB, IE = (β + 1)·IB
Fixed bias
IB = (VCC − 0.7)/RB
Divider bias
IB = (VTH − 0.7)/(RTH + (β + 1)RE)
Thévenin of the divider
VTH = VCC·R2/(R1 + R2), RTH = R1∥R2
Collector loop
VCE = VCC − ICRC − IERE
Saturation
IC(sat) = (VCC − VCE(sat))/RC, IB ≥ IC(sat)/β

Op-amp circuits

Inverting amplifier
Vout = −(Rf/Rin)·Vin
Non-inverting amplifier
Vout = (1 + Rf/R1)·Vin
Summing amplifier
Vout = −Rf(V1/R1 + V2/R2)
Ideal op-amp
V+ = V−, Iin = 0

RC & RL transients

Time constant
τ = RC | τ = L/R
Response
x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ
Capacitor at DC
open circuit; vC cannot jump
Inductor at DC
short circuit; iL cannot jump
Settled
t ≈ 5τ

Method

  1. Find the initial value just after switching: a capacitor voltage and an inductor current cannot jump.
  2. Find the final value long after switching: a capacitor acts as an open circuit, an inductor as a short circuit.
  3. Find the time constant: τ = RC or τ = L/R, using the resistance seen by the capacitor or inductor.
  4. Use x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ.

Series & parallel resistors

Resistors in series
Req = R1 + R2 + …
Resistors in parallel
1/Req = 1/R1 + 1/R2 + …
Two in parallel
Req = R1R2 / (R1 + R2)
Ohm's law
V = I·R
Power
P = V·I = I²R = V²/R

Method

  1. Start at the end of the network furthest from the terminals.
  2. Combine resistors in series by adding them, and resistors in parallel with 1/R = 1/R₁ + 1/R₂ + …
  3. Redraw the circuit after each step.
  4. Repeat until one resistor is left between the terminals.

DC-DC converters

Buck
Vo = D·Vin
Boost
Vo = Vin/(1 − D)
Inverting buck-boost
|Vo| = Vin·D/(1 − D)
Ideal power balance
VinIin = VoIo
Inductor ripple
ΔIL = VL,on·D/(L·f); buck Vin − Vo, boost and buck-boost Vin
Average inductor current
buck Io; boost and buck-boost Io/(1 − D)
Output ripple
buck ΔIL/(8fC); boost and buck-boost Io·D/(fC)
CCM boundary
buck (1 − D)R/(2f); boost D(1 − D)²R/(2f); buck-boost (1 − D)²R/(2f)

Method

  1. Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
  2. Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
  3. Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
  4. For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.

Wheatstone bridge & strain gauges

Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε

Method

  1. Treat the bridge as two voltage dividers across the same supply.
  2. For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
  3. For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
  4. For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

2Practice problems

1.Diodes & transistorsMedium
RC​ = 2.2 kΩβ = 80IC​ = ?RE​ = 680 ΩVCC​ = 18 VR1​ = 68 kΩR2​ = 10 kΩ

An NPN transistor with β = 80 has voltage-divider bias from VCC = 18 V: R₁ = 68 kΩ from VCC to the base and R₂ = 10 kΩ from the base to ground. The collector resistor is RC = 2.2 kΩ and the emitter resistor is RE = 680 Ω. Take VBE = 0.7 V and use the Thévenin equivalent of the divider (do not neglect the base current). Find the collector current IC in mA.

VCC = 18 VR1 = 68 kΩR2 = 10 kΩRC = 2.2 kΩRE = 680 Ωβ = 80
IC = mA
2.Diodes & transistorsHard
V (V)I (mA)0.65330Q = ?

A diode is modelled as 0.65 V in series with 5 Ω (it conducts above 0.65 V). It is in series with a 100 Ω resistor across a 3 V supply. Find the operating current ID where the diode line meets the load line.

Vs = 3 VR = 100 ΩV0 = 0.65 Vrd = 5 Ω
ID = mA
3.Op-amp circuitsMedium
−+Vout​Rf​ = ?R1​ = 47 kΩVin​

Choose the feedback resistor Rf that gives this non-inverting amplifier a voltage gain of 20.

R1 = 47 kΩAv = 20
Rf = kΩ
4.Op-amp circuitsHard
Vin​V1​Vout​stage 1: invertingR1​ = 10 kΩRf1​ = 22 kΩstage 2: non-invertingR2​ = 47 kΩRf2​ = 47 kΩ

Two ideal op-amp stages are connected in cascade: an inverting amplifier (R1, Rf1) followed by a non-inverting amplifier (R2 to ground, Rf2 in the feedback). Both run from ±15 V supplies. The input is Vin = 0.3 V. Find the output voltage Vout.

R1 = 10 kΩRf1 = 22 kΩR2 = 47 kΩRf2 = 47 kΩVin = 0.3 V
Vout = V
5.RC & RL transientsMedium
R = 47 Ωt = 0L150 mHi(t)

The inductor carries a steady current of 2 A. At t = 0 the switch closes the loop through R and the source is removed, so the inductor current decays through R. How long does it take for the current to fall to 0.5 A? Find t.

i(0) = 2 AR = 47 ΩL = 150 mH
t = ms
6.RC & RL transientsHard
+−Vs​15 Vt = 0R = 6.8 kΩC10 µF+−vC​vC​(0) = 30 V

Just before the switch closes at t = 0, the capacitor holds 30 V with the polarity shown. How long does it take for vC to reach 25.5 V? Find t.

Vs = 15 VR = 6.8 kΩC = 10 µFvC(0) = 30 V
t = ms
7.Series & parallel resistorsMedium
R1​ = 10 ΩR3​ = 12 Ω+−V1​12 VR2​3 ΩAR4​6 ΩB

Find the equivalent resistance Req seen by the source V1.

V1 = 12 VR1 = 10 ΩR2 = 3 ΩR3 = 12 ΩR4 = 6 Ω
Req = Ω
8.Series & parallel resistorsHard
R1​ = 8 ΩR3​ = 8 ΩR5​ = 2 Ω+−V1​36 VR2​12 ΩAR4​30 ΩBR6​4 Ω

Find the equivalent resistance Req seen by the source V1.

V1 = 36 VR1 = 8 ΩR2 = 12 ΩR3 = 8 ΩR4 = 30 ΩR5 = 2 ΩR6 = 4 Ω
Req = Ω
9.DC-DC convertersMedium
tiL​Imax​Imin​ΔI = ?DTT2T

An ideal inverting buck-boost converter turns 24 V into −8 V at 25 kHz with L = 68 µH. Find the peak-to-peak inductor ripple current ΔIL.

Vin​ = 24 VVo​ = −8 Vf = 25 kHzL = 68 µH
ΔIL = A
10.DC-DC convertersHard
+−36 VSL = 33 µHC = ?R+−21.6 V

A buck converter turns 36 V into 21.6 V at 100 kHz with L = 33 µH. Find the output capacitance C that limits the peak-to-peak output ripple to 20 mV.

Vin​ = 36 VVo​ = 21.6 Vf = 100 kHzL = 33 µHΔVo = 20 mV
C = µF
11.Wheatstone bridge & strain gaugesMedium
+−9 V300 Ω300 Ω + ΔR300 Ω300 Ωab+−Vab​ = ?

A bridge has four 300 Ω arms and Vs = 9 V. The sensor R₂ increases by ΔR = 15 Ω. Find the exact output Vab in mV.

Vs = 9 VR = 300 ΩΔR = 15 Ω
Vab = mV
12.Wheatstone bridge & strain gaugesHard
+−2.5 V120 Ω − ΔR120 Ω + ΔR120 Ω120 Ωab+−Vo​ = ?

A bridge with 120 Ω arms is excited with 2.5 V and has two active gauges in adjacent arms, one in tension and one in compression (half bridge). The gauge factor is 2.05 and the strain is 800 µε. Find the bridge output Vo in mV.

Vs = 2.5 VGF = 2.05ε = 800 µε
Vo = mV
13.Digital logic: gates, K-maps & flip-flopsMedium
MUXC′I0​CI1​CI2​C′I3​ABS1​S0​F

A 4-to-1 multiplexer has its select inputs S₁ = A and S₀ = B, and its data inputs tied to I₀ = C′, I₁ = C, I₂ = C, I₃ = C′. For how many of the 8 combinations of A, B and C is the output F = 1? Find N.

I₀ = C′I₁ = CI₂ = CI₃ = C′
N =
14.Digital logic: gates, K-maps & flip-flopsHard
CLKJK123456

A positive-edge-triggered JK flip-flop starts with Q = 0 and receives the inputs shown. Click the first clock edge at which Q goes from 1 back to 0.

Q₀ = 0JK
  1. 1clock edge 1
  2. 2clock edge 2
  3. 3clock edge 3
  4. 4clock edge 4
  5. 5clock edge 5
  6. 6clock edge 6

3Solutions

1.Diodes & transistors

Answer: IC = 2.016 mA

BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.

Thévenin equivalent of the divider

VTH = 18·10/(68 + 10) = 2.308 V
RTH = 68·10/(68 + 10) = 8.718 kΩ

Base current

KVL around the base loop; the emitter current is (β + 1)·IB.

IB = (2.308 − 0.7)/(8.718 + 81·0.68) = 25.2 µA

Collector current

IC = 80·25.2 µA = 2.016 mA
IE = 81·25.2 µA = 2.041 mA

Answer

IC = 2.016 mA
2.Diodes & transistors

Answer: ID = 22.38 mA

LED and diode circuits: a forward-biased LED drops roughly its forward voltage VF (about 2 V for red, 3 V for blue or white), whatever the current. A series resistor sets the current: R = (Vs − n·VF)/I for n LEDs in series. With a more exact diode model V = V₀ + I·rd, the operating point is where the diode line meets the load line I = (Vs − V)/R, so I = (Vs − V₀)/(R + rd).

Combine the two equations

3 = 0.65 + I·(100 + 5)

Operating current

ID = 2.35/105 = 22.38 mA
VD = 0.65 + 0.02238·5 = 0.7619 V

Answer

ID = 22.38 mA
3.Op-amp circuits

Answer: Rf = 893 kΩ

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Gain of a non-inverting amplifier

V₋ = V₊ = Vin, and the current through R₁ also flows through Rf, so Vout = Vin·(1 + Rf/R₁).

Av = 1 + Rf/R1
Rf = (20 − 1)·47 = 893 kΩ

Answer

Rf = 893 kΩ
4.Op-amp circuits

Answer: Vout = −1.32 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Gain of each stage

A1 = −Rf1/R1 = −22/10 = −2.2
A2 = 1 + Rf2/R2 = 1 + 47/47 = 2

Stage by stage

V1 = −2.2·0.3 = −0.66 V
Vout = 2·(−0.66) = −1.32 V

Answer

Vout = −1.32 V
5.RC & RL transients

Answer: t = 4.424 ms

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Time constant

τ = L/R = 150 mH / 47 Ω = 3.191 ms

Solve for the time

0.5 = 2·e−t/τ → t = τ·ln(2/0.5)
t = 3.191·ln(4) = 4.424 ms

Answer

t = 4.424 ms
6.RC & RL transients

Answer: t = 24.25 ms

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Initial value, final value, time constant

The capacitor voltage cannot jump, so it starts at its stored value and heads for the source voltage.

vC(0) = 30 V, vC(∞) = Vs = 15 V
τ = R·C = 6.8 kΩ · 10 µF = 68 ms
vC(t) = 15 + (30 − 15)·e−t/τ

Solve for the time

25.5 = 15 + (15)·e−t/τ → e−t/τ = (25.5 − 15)/(30 − 15) = 0.7
t = τ·ln((30 − 15)/(25.5 − 15)) = 68·ln(1.429) = 24.25 ms

Answer

t = 24.25 ms
7.Series & parallel resistors

Answer: Req = 12.57 Ω

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 10 ΩR3​ = 12 Ω+−V1​12 VR2​3 ΩAR4​6 ΩB

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R3 + R4 = 12 + 6 = 18 Ω
R2 ∥ 18 = 3·18/(3+18) = 2.571 Ω
Req = R1 + 2.571 = 10 + 2.571 = 12.57 Ω

Answer

Req = 12.57 Ω
8.Series & parallel resistors

Answer: Req = 14.24 Ω

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 8 ΩR3​ = 8 ΩR5​ = 2 Ω+−V1​36 VR2​12 ΩAR4​30 ΩBR6​4 Ω

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R5 + R6 = 2 + 4 = 6 Ω
R4 ∥ 6 = 5 Ω
R3 + 5 = 13 Ω
R2 ∥ 13 = 6.24 Ω
Req = R1 + 6.24 = 8 + 6.24 = 14.24 Ω

Answer

Req = 14.24 Ω
9.DC-DC converters

Answer: ΔIL = 3.529 A

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 8/(24 + 8) = 0.25

Inductor voltage during the on-time

While S is on, the inductor sits directly across Vin.

VL = 24 V

Ripple current

ΔIL = VL·D/(L·f) = 24·0.25/(68·10⁻⁶·25·10³) = 3.529 A

Answer

ΔIL = 3.529 A
10.DC-DC converters

Answer: C = 163.6 µF

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 21.6/36 = 0.6

Inductor ripple current

ΔIL = (36 − 21.6)·0.6/(33·10⁻⁶·100·10³) = 2.618 A

Capacitance

C = 2.618/(8·100·10³·20·10⁻³) = 163.6 µF

Answer

C = 163.6 µF
11.Wheatstone bridge & strain gauges

Answer: Vab = 109.8 mV

Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.

Node voltages

Va = 9·315/615 = 4.61 V
Vb = 4.5 V

Output

Vab = 109.8 mV

Answer

Vab = 109.8 mV

The linear estimate Vs·ΔR/(4R) = 112.5 mV is 2.5 % too high: a quarter bridge is not quite linear.

12.Wheatstone bridge & strain gauges

Answer: Vo = 2.05 mV

Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.

Relative resistance change

ΔR/R = 2.05·800·10⁻⁶ = 0.00164

Bridge output

Vo = Vs·GF·ε/2 = 2.5·0.00164/2 = 2.05 mV

Answer

Vo = 2.05 mV
13.Digital logic: gates, K-maps & flip-flops

Answer: N = 4

Multiplexer: a 2ⁿ-to-1 multiplexer passes one of its data inputs to the output; the select lines, read as a binary number, pick which one. For a 4-to-1 MUX with selects S₁S₀ = AB, F = A′B′·I₀ + A′B·I₁ + AB′·I₂ + AB·I₃. Tying the data inputs to 0, 1, C or C′ makes the MUX produce any function of A, B and C, which is a common way to build logic with one chip.

Output expression

F = A′B′C′ + A′BC + AB′C + ABC′

Rows with F = 1

ABC = 000, 011, 101, 110
N = 4

Answer

N = 4
14.Digital logic: gates, K-maps & flip-flops

Answer: clock edge 4

Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.

Q after every edge

A JK flip-flop: 00 holds, 01 resets (Q = 0), 10 sets (Q = 1), 11 toggles.

1: J = 0, K = 0 → Q = 0
2: J = 1, K = 0 → Q = 1
3: J = 0, K = 0 → Q = 1
4: J = 1, K = 1 → Q = 0
5: J = 0, K = 1 → Q = 0
6: J = 1, K = 0 → Q = 1

First change from 1 to 0

clock edge 4

Answer

clock edge 4

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