Electronics 1: cram pack

Formula sheets, the key method steps for every topic and 14 practice problems, with full solutions at the back.

New problemsBack to the course

In the print window, choose “Save as PDF” to keep a copy on your device.

1Formulas and methods

Diodes & transistors

Diode (constant drop)
VD = 0.7 V when conducting
Active region
VBE = 0.7 V, IC = β·IB, IE = (β + 1)·IB
Fixed bias
IB = (VCC − 0.7)/RB
Divider bias
IB = (VTH − 0.7)/(RTH + (β + 1)RE)
Thévenin of the divider
VTH = VCC·R2/(R1 + R2), RTH = R1∥R2
Collector loop
VCE = VCC − ICRC − IERE
Saturation
IC(sat) = (VCC − VCE(sat))/RC, IB ≥ IC(sat)/β

Op-amp circuits

Inverting amplifier
Vout = −(Rf/Rin)·Vin
Non-inverting amplifier
Vout = (1 + Rf/R1)·Vin
Summing amplifier
Vout = −Rf(V1/R1 + V2/R2)
Ideal op-amp
V+ = V−, Iin = 0

RC & RL transients

Time constant
τ = RC | τ = L/R
Response
x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ
Capacitor at DC
open circuit; vC cannot jump
Inductor at DC
short circuit; iL cannot jump
Settled
t ≈ 5τ

Method

  1. Find the initial value just after switching: a capacitor voltage and an inductor current cannot jump.
  2. Find the final value long after switching: a capacitor acts as an open circuit, an inductor as a short circuit.
  3. Find the time constant: τ = RC or τ = L/R, using the resistance seen by the capacitor or inductor.
  4. Use x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ.

Series & parallel resistors

Resistors in series
Req = R1 + R2 + …
Resistors in parallel
1/Req = 1/R1 + 1/R2 + …
Two in parallel
Req = R1R2 / (R1 + R2)
Ohm's law
V = I·R
Power
P = V·I = I²R = V²/R

Method

  1. Start at the end of the network furthest from the terminals.
  2. Combine resistors in series by adding them, and resistors in parallel with 1/R = 1/R₁ + 1/R₂ + …
  3. Redraw the circuit after each step.
  4. Repeat until one resistor is left between the terminals.

DC-DC converters

Buck
Vo = D·Vin
Boost
Vo = Vin/(1 − D)
Inverting buck-boost
|Vo| = Vin·D/(1 − D)
Ideal power balance
VinIin = VoIo
Inductor ripple
ΔIL = VL,on·D/(L·f); buck Vin − Vo, boost and buck-boost Vin
Average inductor current
buck Io; boost and buck-boost Io/(1 − D)
Output ripple
buck ΔIL/(8fC); boost and buck-boost Io·D/(fC)
CCM boundary
buck (1 − D)R/(2f); boost D(1 − D)²R/(2f); buck-boost (1 − D)²R/(2f)

Method

  1. Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
  2. Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
  3. Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
  4. For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.

Wheatstone bridge & strain gauges

Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε

Method

  1. Treat the bridge as two voltage dividers across the same supply.
  2. For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
  3. For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
  4. For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.

Digital logic: gates, K-maps & flip-flops

Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states

Method

  1. For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
  2. For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
  3. Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
  4. For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.

2Practice problems

1.Diodes & transistorsMedium
+−18 V270 Ω9.1 V3300 ΩIZ​ = ?

A 9.1 V Zener regulator is fed from 18 V through 270 Ω and supplies a 3300 Ω load. Find the Zener current IZ.

Vin = 18 VVZ = 9.1 VR = 270 ΩRL = 3300 Ω
IZ = mA
2.Diodes & transistorsHard
+−≥ 18 VR = ?5.1 V≤ 25 mA

A 5.1 V Zener regulator must supply up to 25 mA to a load. The input can drop to 18 V, and the Zener needs at least 1 mA to regulate. Find the largest series resistance Rmax that keeps it regulating.

Vin,min = 18 VVZ = 5.1 VIL,max = 25 mAIZ,min = 1 mA
Rmax = Ω
3.Op-amp circuitsMedium
−+Vout​Rf​ = 100 kΩR1​ = 22 kΩVin​ = −2 VRa​ = 4.7 kΩRb​ = 1 kΩ

The op-amp is ideal and runs from ±15 V supplies. Find the output voltage Vout.

Vin = −2 VRa = 4.7 kΩRb = 1 kΩR1 = 22 kΩRf = 100 kΩ
Vout = V
4.Op-amp circuitsHard
−+Vout​C = 0.22 µFVin​ = −1.4 VR = 2.2 kΩ

The integrator uses an ideal op-amp with ±15 V supplies; its output saturates at ±12 V. The capacitor is uncharged when a constant input Vin = −1.4 V is applied at t = 0. How long after t = 0 does the output reach saturation? Find t.

Vin = −1.4 VR = 2.2 kΩC = 0.22 µFVsat = ±12 V
t = ms
5.RC & RL transientsMedium
R = 33 Ωt = 0L150 mHi(t)

The inductor carries a steady current of 0.5 A. At t = 0 the switch closes the loop through R and the source is removed, so the inductor current decays through R. Find the current i at t = 5 ms.

i(0) = 0.5 AR = 33 ΩL = 150 mHt = 5 ms
i = A
6.RC & RL transientsHard
+−Vs​20 Vt = 0R = 10 kΩC220 µF+−vC​vC​(0) = 18 V

Just before the switch closes at t = 0, the capacitor holds 18 V with the polarity shown. How long does it take for vC to reach 19.2 V? Find t.

Vs = 20 VR = 10 kΩC = 220 µFvC(0) = 18 V
t = ms
7.Series & parallel resistorsMedium
R1​ = 8 ΩR3​ = 4 Ω+−V1​24 VR2​5 ΩAR4​4 ΩB

Find the equivalent resistance Req seen by the source V1.

V1 = 24 VR1 = 8 ΩR2 = 5 ΩR3 = 4 ΩR4 = 4 Ω
Req = Ω
8.Series & parallel resistorsHard
R1​ = 3 ΩR3​ = 3 ΩR5​ = 25 Ω+−V1​15 VR2​4 ΩIR2​AR4​4 ΩBR6​2 Ω

Find the current IR2 through R2.

V1 = 15 VR1 = 3 ΩR2 = 4 ΩR3 = 3 ΩR4 = 4 ΩR5 = 25 ΩR6 = 2 Ω
IR2 = A
9.DC-DC convertersMedium
+−12 VSL = ?CR+−3 V

An ideal buck converter turns 12 V into 3 V at a switching frequency of 200 kHz. Find the inductance L that keeps the peak-to-peak inductor ripple current at 0.4 A.

Vin​ = 12 VVo​ = 3 Vf = 200 kHzΔIL = 0.4 A
L = µH
10.DC-DC convertersHard
tiL​Imax​IL​DTT2T

An ideal buck converter turns 12 V into 6 V for a 4 Ω load at 20 kHz. Find the smallest inductance Lcrit for continuous conduction.

Vin​ = 12 VVo​ = 6 Vf = 20 kHzR = 4 Ω
Lcrit = µH
11.Wheatstone bridge & strain gaugesMedium
+−6 VR1​ = 40 ΩR2​ = 50 ΩR3​ = 60 ΩR4​ = 10 ΩabGRg​ = 50 Ω

A galvanometer with a resistance of 50 Ω is connected between a and b of the bridge shown (Vs = 6 V). Find the galvanometer current Ig from a to b, in µA.

Vs = 6 VR1 = 40 ΩR2 = 50 ΩR3 = 60 ΩR4 = 10 ΩRg = 50 Ω
Ig = µA
12.Wheatstone bridge & strain gaugesHard
+−12 V1000 Ω − ΔR1000 Ω + ΔR1000 Ω + ΔR1000 Ω − ΔRab+−Vo​ = ?

A load cell (a full bridge of strain gauges) has a rated output of 1.5 mV/V at its rated load of 200 kg. It is excited with 12 V. Find its output Vo under a load of 50 kg.

1.5 mV/VFrated = 200 kgVs = 12 VF = 50 kg
Vo = mV
13.Digital logic: gates, K-maps & flip-flopsMedium
ABC00011110011001131204050706

Use the Karnaugh map to find the minimal sum-of-products (SOP) form of F(A, B, C) = Σm(0, 2, 3). How many product terms N does it have?

F(A, B, C) = Σm(0, 2, 3)
N =
14.Digital logic: gates, K-maps & flip-flopsHard
ABCD00011110000111100011X3021405X7060121130151141819111110

Find the minimal SOP form of F(A, B, C, D) = Σm(1, 4, 8, 9, 10, 11, 13, 14) + d(3, 7), where d marks the don't-care conditions. How many product terms N does it have?

F(A, B, C, D) = Σm(1, 4, 8, 9, 10, 11, 13, 14) + d(3, 7)
N =

3Solutions

1.Diodes & transistors

Answer: IZ = 30.21 mA

Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.

Resistor current

IR = 8.9/270 = 32.96 mA

Load current

IL = 9.1/3300 = 2.758 mA

Zener current

IZ = 32.96 − 2.758 = 30.21 mA

Answer

IZ = 30.21 mA
2.Diodes & transistors

Answer: Rmax = 496.2 Ω

Zener regulator: a reverse-biased Zener diode holds its voltage VZ while its current stays above a minimum IZ,min. The series resistor R takes the difference between input and output: IR = (Vin − VZ)/R. That current splits between the load, IL = VZ/RL, and the Zener: IZ = IR − IL. Design for the worst cases: the lowest input with the largest load must still leave IZ,min, and the highest input with no load gives the largest Zener power PZ = VZ·IZ.

Worst-case current

IR = 25 + 1 = 26 mA

Largest resistance

Rmax = 12.9/0.026 = 496.2 Ω

Answer

Rmax = 496.2 Ω
3.Op-amp circuits

Answer: Vout = −1.946 V

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Voltage at the + input

V₊ = Vin·Rb/(Ra + Rb) = −2·1/(4.7 + 1) = −0.3509 V

Non-inverting gain

V₋ = V₊, and the current through R₁ also flows through Rf.

Vout = V₊·(1 + Rf/R1) = −0.3509·(1 + 100/22) = −1.946 V

Answer

Vout = −1.946 V
4.Op-amp circuits

Answer: t = 4.149 ms

Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.

Input current and ramp rate

kΩ times µF gives milliseconds.

RC = 2.2 kΩ · 0.22 µF = 0.484 ms
ramp rate = −Vin/(RC) = −(−1.4)/0.484 = 2.893 V/ms

Time to saturation

|Vin|·t/(RC) = Vsat → t = Vsat·RC/|Vin| = 12·0.484/1.4 = 4.149 ms

Answer

t = 4.149 ms
5.RC & RL transients

Answer: i = 0.1664 A

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Time constant

τ = L/R = 150 mH / 33 Ω = 4.545 ms

Decay of the current

i(t) = 0.5·e−5/4.545 = 0.1664 A

Answer

i = 0.1664 A
6.RC & RL transients

Answer: t = 2016 ms

First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.

Initial value, final value, time constant

The capacitor voltage cannot jump, so it starts at its stored value and heads for the source voltage.

vC(0) = 18 V, vC(∞) = Vs = 20 V
τ = R·C = 10 kΩ · 220 µF = 2200 ms
vC(t) = 20 + (18 − 20)·e−t/τ

Solve for the time

19.2 = 20 + (−2)·e−t/τ → e−t/τ = (19.2 − 20)/(18 − 20) = 0.4
t = τ·ln((18 − 20)/(19.2 − 20)) = 2200·ln(2.5) = 2016 ms

Answer

t = 2016 ms
7.Series & parallel resistors

Answer: Req = 11.08 Ω

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 8 ΩR3​ = 4 Ω+−V1​24 VR2​5 ΩAR4​4 ΩB

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R3 + R4 = 4 + 4 = 8 Ω
R2 ∥ 8 = 5·8/(5+8) = 3.077 Ω
Req = R1 + 3.077 = 8 + 3.077 = 11.08 Ω

Answer

Req = 11.08 Ω
8.Series & parallel resistors

Answer: IR2 = 1.695 A

Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.

R1​ = 3 ΩR3​ = 3 ΩR5​ = 25 Ω+−V1​15 VR2​4 ΩAR4​4 ΩBR6​2 Ω

Combine resistors from the far end

Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.

R5 + R6 = 25 + 2 = 27 Ω
R4 ∥ 27 = 3.484 Ω
R3 + 3.484 = 6.484 Ω
R2 ∥ 6.484 = 2.474 Ω
Req = R1 + 2.474 = 3 + 2.474 = 5.474 Ω

Current from the source

The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.

IR1 = V1/Req = 15/5.474 = 2.74 A

Current through R₂

Subtract the drop across R₁ to get the voltage at node A, which is the voltage across R₂.

VA = V1 − IR1·R1 = 15 − 2.74·3 = 6.779 V
IR2 = VA/R2 = 6.779/4 = 1.695 A

Answer

IR2 = 1.695 A
9.DC-DC converters

Answer: L = 28.13 µH

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 3/12 = 0.25

Inductance

L = 9·0.25/(0.4·200·10³) = 28.13 µH

Answer

L = 28.13 µH
10.DC-DC converters

Answer: Lcrit = 50 µH

DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.

Duty cycle

D = 6/12 = 0.5

Boundary condition

Set the average inductor current equal to half the ripple current and solve for L.

Lcrit = (1 − D)·R/(2f)

Critical inductance

Lcrit = (1 − 0.5)·4/(220·10³) = 50 µH

Answer

Lcrit = 50 µH
11.Wheatstone bridge & strain gauges

Answer: Ig = 30648 µA

Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.

Thévenin voltage

Vth = 6·(50/90 − 10/70) = 2.476 V

Thévenin resistance

Rth = R₁∥R₂ + R₃∥R₄ = 30.79 Ω

Galvanometer current

Ig = 2.476/(30.79 + 50) = 30648 µA

Answer

Ig = 30648 µA
12.Wheatstone bridge & strain gauges

Answer: Vo = 4.5 mV

Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.

Full-scale output

1.5·12 = 18 mV

Output at this load

Vo = 18·50/200 = 4.5 mV

Answer

Vo = 4.5 mV
13.Digital logic: gates, K-maps & flip-flops

Answer: N = 2

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

ABC00011110011001131204050706

Group the 1s

Every group is a rectangle of 2ᵏ cells; edge cells are neighbours of the cells on the opposite edge.

A′C′
A′B

Minimal SOP form

F = A′C′ + A′B
N = 2

Answer

N = 2
14.Digital logic: gates, K-maps & flip-flops

Answer: N = 5

Karnaugh maps: the cells are ordered in Gray code (00, 01, 11, 10), so neighbouring cells, including the ones across the edges, differ in exactly one variable. Group the 1s in rectangles of 1, 2, 4, 8 or 16 cells, as large as possible and as few as possible, until every 1 is covered. Each group is one product term: the variables that stay constant inside it. A group of 2ᵏ cells loses k variables. Don't-cares (X) may be used to make groups bigger but never have to be covered. Grouping the 0s instead gives the minimal POS form.

Prime implicants

The largest groups that can be formed from 1s and Xs.

B′D, AC′D, ACD′, AB′, A′BC′D′
ABCD00011110000111100011X3021405X7060121130151141819111110

Minimal cover

F = B′D + AC′D + ACD′ + AB′ + A′BC′D′
N = 5

Answer

N = 5

ExamProblems · examproblems.com/courses/electronics-1