Identify the converter (buck, boost or buck-boost) and the duty cycle D from the voltage ratio.
Use volt-second balance on the inductor: the average inductor voltage over a period is zero.
Find the inductor voltage while the switch is on, then ΔIL = VL·D/(L·f).
For the output ripple, find the charge that flows in and out of the capacitor; for the CCM boundary, set the average inductor current equal to ΔIL/2.
Wheatstone bridge & strain gauges
Divider voltages
Va = VsR2/(R1 + R2), Vb = VsR4/(R3 + R4)
Output
Vab = Va − Vb
Balance
R1/R2 = R3/R4
Slide-wire bridge
R/Rx = l/(100 − l)
Thévenin resistance
Rth = R1∥R2 + R3∥R4
Gauge factor
ΔR/R = GF·ε
Bridge output
quarter Vs·GF·ε/4, half Vs·GF·ε/2, full Vs·GF·ε
Small change, one arm
Vab ≈ Vs·ΔR/(4R)
Stress
σ = E·ε
Method
Treat the bridge as two voltage dividers across the same supply.
For balance, set R₁/R₂ = R₃/R₄ and solve for the unknown resistor.
For an unbalanced bridge, find Va and Vb from the dividers and subtract; use the Thévenin equivalent when a meter loads the output.
For strain gauges, convert strain to ΔR/R = GF·ε and use Vs·GF·ε/4, /2 or ×1 for a quarter, half or full bridge.
Digital logic: gates, K-maps & flip-flops
Basic gates
A·B, A + B, A′, (A·B)′, (A + B)′, A ⊕ B
Boolean rules
X + X′ = 1, X·X′ = 0, X + XY = X, XY + XY′ = X
De Morgan
(X·Y)′ = X′ + Y′, (X + Y)′ = X′·Y′
Karnaugh map order
00, 01, 11, 10 (Gray code)
Group of 2ᵏ cells
loses k variables
4-to-1 multiplexer
F = A′B′I0 + A′BI1 + AB′I2 + ABI3
Flip-flops
D: Q⁺ = D, T: Q⁺ = T ⊕ Q, JK: Q⁺ = JQ′ + K′Q
Counters
n-bit: 2ⁿ states; mod-N: smallest n with 2ⁿ ≥ N; fout = fclk/N
Ripple counter
fmax = 1/(n·tpd)
Ring and Johnson counters
n and 2n states
Method
For a circuit, work from the inputs to the output one gate at a time and write the value on every wire, or write its expression and fill in the truth table.
For simplification, put the 1s (and the don’t-cares as X) into a Karnaugh map with Gray-code rows and columns: 00, 01, 11, 10.
Cover the 1s with as few and as large groups of 1, 2, 4, 8 or 16 cells as possible, wrapping round the edges; each group is one product term made of the variables that stay constant. Group the 0s for the POS form.
For flip-flops and counters, read the inputs at each active clock edge, write the state after every edge, and remember that an n-bit counter wraps round after 2ⁿ states.
2Practice problems
1.Diodes & transistorsMedium
An NPN transistor with β = 50 is biased by a base resistor RB = 270 kΩ from the supply VCC = 12 V. The collector resistor is RC = 1.2 kΩ and the emitter is grounded. Take VBE = 0.7 V and assume the transistor is in the active region. Find the collector current IC in mA.
VCC = 12 VRB = 270 kΩRC = 1.2 kΩβ = 50VBE = 0.7 V
IC = mA
2.Diodes & transistorsHard
An NPN transistor with β = 80 switches a 100 Ω load resistor connected between VCC = 9 V and its collector. The emitter is grounded. The base is driven from a 3.3 V logic output through a base resistor RB. Take VBE = 0.7 V and VCE(sat) = 0.2 V. For reliable switching, design for a base current 4 times the minimum needed for saturation. Find RB in kΩ.
The op-amp is ideal and runs from ±15 V supplies; its output saturates at ±13 V. The non-inverting amplifier is driven by a sine wave. Find the largest input amplitude Vin,max (peak value) for which the output does not clip.
R1 = 4.7 kΩRf = 10 kΩVsat = ±13 V
Vin,max = V
4.Op-amp circuitsHard
The integrator uses an ideal op-amp with ±15 V supplies; its output saturates at ±14 V. The capacitor is uncharged when a constant input Vin = 2.4 V is applied at t = 0. How long after t = 0 does the output reach saturation? Find t.
Vin = 2.4 VR = 22 kΩC = 1 µFVsat = ±14 V
t = ms
5.RC & RL transientsMedium
The inductor carries no current before the switch closes at t = 0. Find the current i at t = 5 ms.
Vs = 12 VR = 20 ΩL = 47 mHt = 5 ms
i = A
6.RC & RL transientsHard
Just before the switch closes at t = 0, the capacitor holds 15 V with the polarity shown. Find the capacitor voltage vC at t = 120 ms.
Vs = 24 VR = 2.2 kΩC = 68 µFvC(0) = 15 Vt = 120 ms
vC = V
7.Series & parallel resistorsMedium
Find the current IR1 delivered by the source, which flows through R1.
V1 = 15 VR1 = 10 ΩR2 = 20 ΩR3 = 4 ΩR4 = 4 Ω
IR1 = A
8.Series & parallel resistorsHard
Find the current IR1 delivered by the source, which flows through R1.
An ideal inverting buck-boost converter turns 9 V into −21 V at 100 kHz with L = 220 µH. Find the peak-to-peak inductor ripple current ΔIL.
Vin = 9 VVo = −21 Vf = 100 kHzL = 220 µH
ΔIL = A
10.DC-DC convertersHard
An ideal boost converter turns 9 V into 22.5 V for an 8 Ω load at 100 kHz. The output capacitor is 100 µF. Find the peak-to-peak output voltage ripple ΔVo in mV.
A bridge has four 100 Ω arms and Vs = 5 V. The sensor R₂ increases by ΔR = 0.4 Ω. Using the small-change approximation, find the output Vab in mV.
Vs = 5 VR = 100 ΩΔR = 0.4 Ω
Vab = mV
12.Wheatstone bridge & strain gaugesHard
A load cell (a full bridge of strain gauges) has a rated output of 2.5 mV/V at its rated load of 50 kg. It is excited with 5 V. Find its output Vo under a load of 12.5 kg.
A 4-to-1 multiplexer has its select inputs S₁ = A and S₀ = B, and its data inputs tied to I₀ = 0, I₁ = 0, I₂ = 0, I₃ = C′. For how many of the 8 combinations of A, B and C is the output F = 1? Find N.
I₀ = 0I₁ = 0I₂ = 0I₃ = C′
N =
14.Digital logic: gates, K-maps & flip-flopsHard
A positive-edge-triggered D flip-flop starts with Q = 0 and receives the inputs shown at 7 rising clock edges. How many times N does Q change state?
Q₀ = 0D
N =
3Solutions
1.Diodes & transistors
Answer: IC = 2.093 mA
BJT bias point: in the active region VBE = 0.7 V, IC = β·IB and IE = (β + 1)·IB. Find IB from the base loop with KVL, then IC, then VCE from the collector–emitter loop. A voltage divider at the base is replaced by its Thévenin equivalent VTH = VCC·R₂/(R₁ + R₂), RTH = R₁∥R₂; an emitter resistor appears (β + 1) times larger in the base loop.
Check: VCE = 9.489 V is well above 0.2 V, so the transistor is indeed active.
2.Diodes & transistors
Answer: RB = 0.5909 kΩ
BJT as a switch: to switch a load fully on, the transistor is driven into saturation, where VCE = VCE(sat) and the collector current is set by the load: IC(sat) = (VCC − VCE(sat))/RC. Saturation needs at least IB = IC(sat)/β. If the base current is smaller, the transistor stays active and IC = β·IB.
Collector current in saturation
IC(sat) = (9 − 0.2)/100 = 88 mA
Minimum base current
IB(min) = IC(sat)/β = 88/80 = 1100 µA
Design base current
IB = 4·1100 µA = 4400 µA
Base resistor
RB = (3.3 − 0.7)/IB = 2.6 V/4.4 mA = 0.5909 kΩ
Answer
RB = 0.5909 kΩ
3.Op-amp circuits
Answer: Vin,max = 4.156 V
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Gain
Av = 1 + Rf/R1 = 1 + 10/4.7 = 3.128
Largest input before clipping
Vin,max = Vsat/|Av| = 13/3.128 = 4.156 V
Answer
Vin,max = 4.156 V
4.Op-amp circuits
Answer: t = 128.3 ms
Ideal op-amp rules: with negative feedback, the op-amp drives its output so that its two inputs sit at the same voltage (V₋ = V₊), and no current flows into either input. Writing KCL at the inverting input with these two facts gives the output.
Input current and ramp rate
kΩ times µF gives milliseconds.
RC = 22 kΩ · 1 µF = 22 ms
ramp rate = −Vin/(RC) = −2.4/22 = −0.1091 V/ms
Time to saturation
|Vin|·t/(RC) = Vsat → t = Vsat·RC/|Vin| = 14·22/2.4 = 128.3 ms
Answer
t = 128.3 ms
5.RC & RL transients
Answer: i = 0.5285 A
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Time constant and final current
Long after the switch closes the inductor behaves like a short circuit, so the final current is set by R alone.
First-order transients: in a circuit with one capacitor or one inductor, every voltage and current moves exponentially from its initial value to its final value: x(t) = x(∞) + [x(0) − x(∞)]·e−t/τ, with τ = RC or τ = L/R. After about 5τ the circuit has settled.
Initial value, final value, time constant
The capacitor voltage cannot jump, so it starts at its stored value and heads for the source voltage.
vC(0) = 15 V, vC(∞) = Vs = 24 V
τ = R·C = 2.2 kΩ · 68 µF = 149.6 ms
vC(t) = 24 + (15 − 24)·e−t/τ
Voltage at the given time
vC(120) = 24 + (−9)·e−120/149.6 = 19.96 V
Answer
vC = 19.96 V
7.Series & parallel resistors
Answer: IR1 = 0.9545 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R3 + R4 = 4 + 4 = 8 Ω
R2 ∥ 8 = 20·8/(20+8) = 5.714 Ω
Req = R1 + 5.714 = 10 + 5.714 = 15.71 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 15/15.71 = 0.9545 A
Answer
IR1 = 0.9545 A
8.Series & parallel resistors
Answer: IR1 = 1.394 A
Series and parallel resistors: in series the same current flows through each resistor and R = R₁ + R₂ + …. In parallel each resistor has the same voltage and 1/R = 1/R₁ + 1/R₂ + …. A ladder network is reduced one pair at a time until a single equivalent resistance remains.
Combine resistors from the far end
Start at the end farthest from the source and work back towards it. Resistors carrying the same current are in series; resistors across the same two nodes are in parallel.
R5 + R6 = 25 + 20 = 45 Ω
R4 ∥ 45 = 5.294 Ω
R3 + 5.294 = 11.29 Ω
R2 ∥ 11.29 = 5.818 Ω
Req = R1 + 5.818 = 20 + 5.818 = 25.82 Ω
Current from the source
The source sees only Req, so Ohm’s law gives the current it delivers. That current flows through R₁.
IR1 = V1/Req = 36/25.82 = 1.394 A
Answer
IR1 = 1.394 A
9.DC-DC converters
Answer: ΔIL = 0.2864 A
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 21/(9 + 21) = 0.7
Inductor voltage during the on-time
While S is on, the inductor sits directly across Vin.
VL = 9 V
Ripple current
ΔIL = VL·D/(L·f) = 9·0.7/(220·10⁻⁶·100·10³) = 0.2864 A
Answer
ΔIL = 0.2864 A
10.DC-DC converters
Answer: ΔVo = 168.8 mV
DC-DC converters: a switch S turns on for the fraction D of each period T = 1/f. In steady state the average inductor voltage is zero (volt-second balance), which gives the ideal conversion ratios in continuous conduction: buck Vo = D·Vin, boost Vo = Vin/(1 − D), inverting buck-boost |Vo| = Vin·D/(1 − D). An ideal converter keeps the power: Vin·Iin = Vo·Io. While S is on the inductor current rises by ΔIL = VL·D·T/L, with VL = Vin − Vo for the buck and Vin for the boost and buck-boost. The output ripple is ΔVo = ΔIL/(8fC) for the buck and Io·D/(fC) for the boost and buck-boost. The inductor current just touches zero (the CCM boundary) when the average inductor current equals ΔIL/2.
Duty cycle
D = 1 − 9/22.5 = 0.6
Load current
Io = 22.5/8 = 2.813 A
Output ripple
ΔVo = 2.813·0.6/(100·10³·100·10⁻⁶) = 168.8 mV
Answer
ΔVo = 168.8 mV
11.Wheatstone bridge & strain gauges
Answer: Vab = 5 mV
Wheatstone bridge: two voltage dividers share one supply Vs. The left divider R1–R2 gives Va = Vs·R2/(R1 + R2) and the right divider R3–R4 gives Vb = Vs·R4/(R3 + R4); the output is Vab = Va − Vb. The bridge is balanced (Vab = 0, no current in the meter) when R1/R2 = R3/R4, that is R1·R4 = R2·R3. Seen from the output, the bridge is a Thévenin source with Rth = R1∥R2 + R3∥R4.
Relative change
ΔR/R = 0.4/100 = 0.004
Linearised output
Vab ≈ 5·0.004/4 = 5 mV
Answer
Vab = 5 mV
The exact value is 4.99 mV; the approximation is good while ΔR/R is small.
12.Wheatstone bridge & strain gauges
Answer: Vo = 3.125 mV
Strain gauges: a gauge changes its resistance with strain: ΔR/R = GF·ε, where the gauge factor GF is about 2 for metal foil. In a bridge with all arms equal to R, one active gauge (quarter bridge) gives Vo ≈ Vs·GF·ε/4. Two active gauges with opposite strains in adjacent arms (half bridge) give Vs·GF·ε/2, and four (full bridge) give Vs·GF·ε. Stress follows from Hooke’s law, σ = E·ε. Load cells state their sensitivity in mV/V: the output at full load per volt of excitation.
Full-scale output
2.5·5 = 12.5 mV
Output at this load
Vo = 12.5·12.5/50 = 3.125 mV
Answer
Vo = 3.125 mV
13.Digital logic: gates, K-maps & flip-flops
Answer: N = 1
Multiplexer: a 2ⁿ-to-1 multiplexer passes one of its data inputs to the output; the select lines, read as a binary number, pick which one. For a 4-to-1 MUX with selects S₁S₀ = AB, F = A′B′·I₀ + A′B·I₁ + AB′·I₂ + AB·I₃. Tying the data inputs to 0, 1, C or C′ makes the MUX produce any function of A, B and C, which is a common way to build logic with one chip.
Output expression
F = ABC′
Rows with F = 1
ABC = 110
N = 1
Answer
N = 1
14.Digital logic: gates, K-maps & flip-flops
Answer: N = 3
Flip-flops and counters: a flip-flop changes only at the active clock edge. D copies its input (Q⁺ = D); T toggles when T = 1; JK holds for 00, resets for 01, sets for 10 and toggles for 11. An n-bit binary counter has 2ⁿ states and counts modulo 2ⁿ; a mod-N counter goes 0, 1, …, N − 1 and back to 0, and needs the smallest n with 2ⁿ ≥ N flip-flops. Each stage of a ripple counter halves the frequency, so the last output of a mod-N counter runs at fclk/N. A Johnson counter of n flip-flops has 2n states, a ring counter n.
Q after every edge
A D flip-flop copies D at each rising edge: Q⁺ = D.