The inputs of the logic circuit are A = 0, B = 1 and C = 0. Exactly one of its gates has the output 0. Click that gate.
- 1N1
- 2G1
- 3G2
The inputs of the logic circuit are A = 0, B = 1 and C = 0. Exactly one of its gates has the output 0. Click that gate.
The propagation delay of every gate is written under it. Find the worst-case propagation delay tpd from the inputs to the output F.
Use the Karnaugh map to find the minimal product-of-sums (POS) form of F(A, B, C, D) = Σm(0, 1, 3, 5, 6, 14). How many sum terms (factors) N does it have?
In this Karnaugh map exactly one 1 has no neighbouring 1, so it stays a group of one cell (a full minterm of four literals) in the minimal SOP form. Neighbours across the map edges count. Click that cell.
A positive-edge-triggered D flip-flop starts with Q = 0 and receives the inputs shown. Click the first clock edge at which Q goes from 1 back to 0.
Find the minimal SOP form of F(A, B, C, D) = Σm(1, 6, 9, 12, 15) + d(2, 10, 11), where d marks the don't-care conditions. How many product terms N does it have?
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