Digital logic: gates, K-maps & flip-flops worksheet with answers

Click the cell of the 4-variable Karnaugh map that belongs to minterm m15 (variables A, B, C, D with A the most significant bit).

1. 1AB = 00, CD = 00
2. 2AB = 00, CD = 01
3. 3AB = 00, CD = 11
4. 4AB = 00, CD = 10
5. 5AB = 01, CD = 00
6. 6AB = 01, CD = 01
7. 7AB = 01, CD = 11
8. 8AB = 01, CD = 10
9. 9AB = 11, CD = 00
10. 10AB = 11, CD = 01
11. 11AB = 11, CD = 11
12. 12AB = 11, CD = 10
13. 13AB = 10, CD = 00
14. 14AB = 10, CD = 01
15. 15AB = 10, CD = 11
16. 16AB = 10, CD = 10

The inputs of the logic circuit are A = 1, B = 1 and C = 1. Exactly one of its gates has the output 1. Click that gate.

1. 1N1
2. 2G1
3. 3G2

A 4-to-1 multiplexer has its select inputs S₁ = A and S₀ = B, and its data inputs tied to I₀ = C′, I₁ = C, I₂ = C′, I₃ = C′. For how many of the 8 combinations of A, B and C is the output F = 1? Find N.

Use the Karnaugh map to find the minimal sum-of-products (SOP) form of F(A, B, C, D) = Σm(0, 2, 3, 4, 5, 7, 9, 11, 12, 14). How many product terms N does it have?

A 4-bit shift register Q₃Q₂Q₁Q₀ holds 0101. At every clock edge the bits shift one place to the right (Q₃ → Q₂ → Q₁ → Q₀, Q₀ is lost) and the serial input enters Q₃. The serial input is 0, 0, 0, 1, 0 at the 5 edges. Give the final state Q = Q₃Q₂Q₁Q₀ as a decimal number.

A positive-edge-triggered T flip-flop starts with Q = 0 and receives the inputs shown at 6 rising clock edges. How many times N does Q change state?